1. Field of the Invention
This invention relates to the field of processors for data-processing systems, and in particular to a method for increasing the robustness of an interrupt handling mechanism.
2. Description of the Related Art
In a data-processing system the basic logical arithmetic computational operations are performed by the processor. The processors use a processor core operating under control of program instruction words, which when decoded serve to generate control signals to control the different elements within the processor core to perform the necessary functions to achieve the processing specified in the program instruction word. For this purpose there is provided within the processor core a number of registers and logic circuits. The processor registers are used to receive, hold, and transmit information (data and instructions) used by the processor. Several different types of registers are provided within the typical processor core. For example, an accumulator register temporarily stores data and accumulates the results of logical or arithmetic operations. A program counter stores the address of the next instruction in memory to be executed. An instruction register stores the instruction code (also known as the operation code) portion of instruction which is currently being executed by the processor, and an address register or data counter stores the operand portion of the currently executing instruction.
The processor executes the instructions of a program in a sequence known as a program control flow. As the processor moves through the program control flow, it performs the functionality specified by the program. The processor is designed to move through the program control flow in a manner specified by the program, except when an exception occurs. Exceptions cause the processor to (a) mark the current point in the program control flow, and (b) start executing an exception routine. Possible triggers of an exception include illegal conditions in the processor and processor interrupts. If one of these triggers occurs, it is desired that the processor attempt to resolve the exception, and the manner for resolving the exception is specified by the exception routine. The exception routine often begins by determining the source of the exception then taking appropriate action. Typically this involves storing the contents of the registers and invoking a handling routine which is designed to handle the source of the exception. For interrupts, the handling routines typically treat the interrupt as a request for a desired service, perform the service, and then cause the processor to return to the marked point in the program control flow. For illegal conditions, the handling routines may halt the program or search for a specified corrective action to take.
At any given instant in complex or pipelined processors, multiple modules of the processor can be actively involved in the executing of the program control flow, and each must be notified when an exception trigger occurs before the transfer of control to the exception routine can be fully accomplished. The notification mechanism to these modules can be different, and a spurious assertion of an exception trigger (i.e. an interrupt) may cause some modules to be notified while others are not. If any of these modules is not notified, the processor enters an undefined state. It is desirable to prevent this from happening without redesigning the carefully optimized asynchronous interaction between the various modules.